www.fairchildsemi.com ? 2010 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/27/10 AN-6206 primary-side synchronous rectifier (sr) trigger solution for dual-forward converter introduction in any switching converter, rectifier diodes are used to obtain dc output voltage. the conduction loss of diode rectifier contributes significantly to the overall power losses in a power supply; especially in low output voltage applications, such as personal computer (pc) power supplies. the conduction loss of a rectifier is proportional to the product of its forward-voltage drop and the forward conduction current. using synchronous rectification (sr) where the rectifier diode is replaced by mosfet with proper on resistance (rds on ), the forward-voltage drop of a synchronous rectifier can be lower than that of a diode rectifier and, consequently, the rectifier conduction loss can be reduced. the highly integrated fan6210 is a primary-side sr controller for dual-forward convert er that provides control signals for the secondary-side sr driver fan6206. fan6210 also provides drive signal for the primary-side power switches by using an output signal from the pwm controller. fan6210 can be combined with any pwm controller that can drive a dual-forward converter. to obtain optimal timing for the sr drive signals, transformer winding voltage is also monitored. to improve light-load efficiency, green-mode operation is employed, which disables the sr turn-on trigger signal, minimizing gate drive power consumption at light-load condition. this application note describes the design procedure of sr circuit using fan6210 and fan6206. the guidelines for printed circuit board (pcb) layout and a design example with experiment results are also presented. rdly det xp gnd sin fan6210 v in v o 1 2 3 4 8 7 6 5 xn sout vdd pwm control signal (from pwm controller) pfc stage v ac from power supply of pwm controller sp vdd lpc1 gate1 sn 1 2 3 4 8 7 6 5 lpc2 gnd gate2 fan6206 drv drv r 1 r 5 q 1 q 2 pt r 2 r 3 r 4 r 7 r 6 r 8 r 9 d 1 d 2 d 3 d 4 d 5 d 6 l o n:1 c 2 c bulk c 1 figure 1. typical application
AN-6206 application note ? 2010 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/27/10 2 1. fan6210 external component setting figure 2 and figure 3 show the simplified schematic of two switch forward converters and their waveforms. the rectifying sr (sr1) should be turned on right after the primary-side mosfets are turned on. then, sr1 should be turned off right before the primary-side mosfets are turned off. the freewheeling sr (sr2) should be turned on right after the primary-side mosfets are turned off. then, sr2 should be turned off right before the primary-side mosfets are turned on. the primary-side sr trigger controller fan6210 generates xn and xp signals, where xn rising edge triggers the turn-off of sr and xp rising edge triggers the turn-on of sr. fan6210 generates xp and xn signals two times for each in one switching cycle and fan6206 in the secondary side determines which sr mosfet should be controlled for each xp and xn signals within one switching cycle. figure 2. simplified circuit diagram of dual-forward converter figure 3. key waveforms of dual-forward converter figure 4 and figure 5 show the detailed timing diagrams of xp and xn for the rising edge and falling edge of the sin signal. the delay from the rising edge of sout to xp signal rising edge (t dly_xp ) is programmable using r 1 , as shown in figure 1. the linear relationship between r 1 and t dly_xp is shown in figure 6. the transformer winding voltage is much higher than the voltage rating of fan6210 during pwm turn-on time. therefore, r 2 and d 1 are used to block the high voltage, as shown in figure 1. since there is a 400ns det falling-edge detection window after sout falls to prevent mis- triggering of xp in dcm operation, too large value of r 2 does not trigger xp properly due to too large rc time delay. it is typical to use 10k ? ~33k ? for r 2 . the other requirement for triggering xp signal is that the high level of the det signal must be higher than 3v. to shorten the falling time from high level to low level, the breakdown voltage of zener diode d 2 is recommended as 5~6v. figure 4. timing diagram during pwm rising edge figure 5. timing diagram during pwm falling edge
AN-6206 application note ? 2010 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/27/10 3 figure 6. programmable delay with resistor r 1 2. pulse transformer (pt) the differential sr control xp-xn is delivered from fan6210 to fan6206 thro ugh a pulse transformer ( pt ), as shown in figure 7. for the proper signal transfer, the core should have high initial permeability ( i ). to separate primary-side and secondary-side windings, isolation is also necessary. it is typical to have the same number of turns for the primary and secondary to maximize the coupling. as the inductance of the winding decreases, the magnetizing increases, causing the voltage drop in the primary winding, as shown in figure 8. the high level of xp or xn signal should be higher than 4v to ensure proper sr gate driving. meanwhile, too many turns may increase the inter-winding capacitance and, therefore, the inductance value should be determined properly. typically, the inductance value is recommended as 100 h~300 h. figure 7. pulse transformer structure figure 8. slope difference between different turn number on xp signal to protect the xp and xn pins from transient voltage spikes; components r 3 , r 4 , d 3 , d 4 , d 5 , and d 6 are necessary (shown in figure 1). r 3 and r 4 are recommended as 10 ? . d 3 ~ d 6 are chosen as fairchild diode 1n4148. at the secondary side, r 5 is connected between the sp and sn pins for reducing the overshoot caused by pt . the proper value of r 5 is 1k ? ~10k ? for most of applications. fan6206 external components setting fan6206 needs only four resistors to achieve winding detection and linear-predict control (lpc). voltage divider with r 6 and r 7 detects the voltage across the drain-to-source terminal of q 1 , while the other divider with r 8 and r 9 detects the voltage across the drain-to-source terminal of q 2 . figure 9 shows the typical waveform under ccm operation, which includes rectifying sr mosfet drain voltage (v ds-r ), freewheeling sr mosfet drain voltage ( v ds-f ), inductor current ( i lo ), sr control signals (sp & sn), and sr gate signals. the detected signal on lpc1 and lpc2 pin determines the operation of synchronous rectification. the voltage divider scale-down factors are defined as: 7 lpc1 67 r ratio = r +r (1) 9 lpc2 89 r ratio = r +r (2) 2.1 rectifying sr gate drive linear-predict control (lpc) is not essential for rectifying sr because rectifying sr is always turned off by the sn signal. voltage divider with r 6 and r 7 is used to detect the high/low status of v ds-r , as shown in figure 9. the high level threshold voltage for lpc1 is 2v, so the plateau voltage of lpc1 should be higher than 2v. to guarantee stable operation, the minimum plateau voltage of lpc1 is suggested to be 3v. however, lpc pin is a low- voltage pin, so the proper operation range is from 3v to 5v. therefore: in lpc1 v 3 AN-6206 application note ? 2010 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/27/10 4 in v n in v n figure 9. typical waveform in ccm operation 2.2 freewheeling sr gate drive once the forward converter enters discontinuous conduction mode (dcm) at light-load condition, the current through the freewheeling sr decreases to zero before the turn-off command by xn signal is given. thus, the current can flow in the reverse direction if the freewheeling sr is not turned off before the current changes direction. lpc function is necessary to turn off the free-wheeling sr before the output inductor current reaches zero in dcm operation. voltage divider with r 8 and r 9 determines the turn-off timing of freewheeling sr. for proper lpc operation, the lpc pin voltage should be normalized to the nominal output voltage. the scale-down factor of the voltage divider should be 1/ v o . for 12v output application, the proper value of ratio lpc2 is: lpc2 11 AN-6206 application note ? 2010 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/27/10 5 printed circuit board layout in figure 12, the power traces are marked as bold lines. good pcb layout improves power system efficiency, minimizes excessive emi, and prevents the power supply from being disrupted during surge/esd tests. guidelines ? for pc power applications, the pfc/pwm combination controller is usually separated from main board and is applied at a daughter board. fan 6210 is also recommended to be placed on the same daughter board. as indicated by 1 and 2 , fan6210 control circuits? ground should be connected together and to the gnd pin of fan6210 first, then the gnd pin to ground of pfc/pwm combination controller. ? as indicated by 3 and 4 , pfc/pwm combination controller?s ground and pwm mosfets? ground are connected to the negative terminal of c bulk . keep trace 4 short, direct, and wide. ? a y-cap between the primary and secondary is necessary for pc power applications. as indicated by 5 and 6 , the y-cap is suggested on the low-side, where it is between the negative terminal of c bulk and case. connecting trace 6 directly to case is helpful to surge immunity. according to the safety requirements, the creepage between the two pointed ends should be at least 5mm. the y-cap should be far away from pt . ? as indicated by 8 , fan6206 control circuits? ground should be connected together, then to the gnd pin of fan6206. ? as indicated by 9 , the gnd pin of fan6206 should be connected to the source of q 1 and q 2 separately. keeping trace 9 short and direct can maintain the ground level between mosfet and gnd pin closed. thus, the sr control signal can be kept away from error triggering. ? as indicated by 10 , the source terminals of q 1 and q 2 are connected to the negative terminal of c o . keep trace 10 short, direct, and wide. ? as indicated by 11 , v o is connected to the supervisor ic. as indicated by 12 , the power supply source of fan6206?s vdd pin is connected to the detection terminal of supervisor ic. trace 11 should be long and far away from v o terminal. it?s helpful to prevent lpc mechanism from output current interference. ? as indicated by 7 , the negative terminal of c o is connected to case directly. figure 12. layout considerations
AN-6206 application note ? 2010 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/27/10 6 design example the following example is a 12v/300w pc power supply, in which the dual-forward topology is used. as figure 13 shows, the fan4801 integrated ccm pfc/pwm combination controller is used as the controller for both pfc stage and pwm stage. the basic system parameters are listed in table 1.the two- level v bulk is derived from fan4801. the typical voltage level for v bulk is 380v; but under low-line and light-load condition, v bulk is 310v for decreasing power loss at the pfc stage. the typical switching frequency ( f s ) is 65khz for both pfc and pwm stage. in a typical pc power application, multi-output is necessary. if the 12v output terminal is used to generate other output terminals, sg6520 can be the proper supervisor ic. the power supply of the supervisor is from 5v standby output terminal. flyback topology is the general structure for standby power. the following measurements include standby loading. fan6751 is chosen to be the pwm controller of standby stage. from the specification, all cr itical components are treated and final measurement results are given. base on the design guideline, the critical parameters are calculated and summarized in table 2. table 1. system specification input input voltage range 90~264v ac line frequency range 47~63hz output voltage of pfc stage ( v bulk ) 310v / 380v output output voltage ( v o ) 12v output power ( p o ) 300w typical switching frequency ( f s ) 65khz in addition to low-line and light-load condition, v bulk is boosted to 380v. the turn ratio n for of tx 1 is 11, hence the v ds voltage during pwm turn-on period is 380/11=34.55v. according to equation 4, ratio lpc2 = 1/11.5. the divided voltage on lpc2 is 3.00v. according to equation 3, the plateau divided voltage on lpc1 during pwm turn-off period should be between 3v~5v. select ratio lpc2 = 1/7.8, then the divided voltage is 4.43v. select r 9 = 10k ? and r 8 = 105k ? , then r 7 = 10k ? and r 6 = 68k ? . under low-line and light-load condition, v bulk is decreased to 310v. the divided voltage on lpc2 is 2.45v, while the divided voltage on lpc1 is 3.61v. rdly det xp gnd sin =12v 1 2 3 4 8 7 6 5 xn sout vdd opwm (from fan4801) pfc stage (controlled by fan4801) from vdd of fan4801 ipwm (to fan4801) sp vdd lpc1 gate1 sn 1 2 3 4 8 7 6 5 lpc2 gnd gate2 + - supervisor power supply is from 5v standby output figure 13. complete circuit diagram
AN-6206 application note ? 2010 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/27/10 7 table 2. bill of materials part value note part value note resistor inductor r 1 8.2k 1/8w l 1 73h r 2 10k 1/4w l 2 1.8h r 3 10 1/8w diode r 4 10 1/8w d 1 fr107 r 5 2k 1/8w d 2 zenor diode/5.6v r 6 68k 1/8w d 3 1n4148 r 7 10k 1/8w d 4 1n4148 r 8 105k 1/8w d 5 1n4148 r 9 10k 1/8w d 6 1n4148 r 10 10k 1/8w d 7 1n4148 r 11 10k 1/8w d 8 1n4148 r 12 4.7 1/8w d 9 uf1007 r 13 4.7 1/8w d 10 uf1007 r 14 10k 1/8w mosfet r 15 10k 1/8w q 1 fdp5800 r 16 0.15 2w q 2 fdp5800 r 17 3k 1/8w q 3 fcp20n60 r 18 38.3k 1/8w q 4 fcp20n60 r 19 10k 1/8w transformer r 20 1k 1/8w tx 1 66:6 primary 20mh capacitor tx 2 1:1 primary 160 h c 1 100nf 50v tx 3 1:1.2 primary 300 h c 2 100nf 50v ic c 3 470pf 25v u 1 fan6210 c 4 100nf 50v u 2 fan6206 c 5 270 f 450v u 3 pc817 c 6 1 f 50v u 4 tl431 c 7 3300 f 16v c 8 3300 f 16v c 9 4.7nf/250v y-capacitor
AN-6206 application note ? 2010 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/27/10 8 figure 14 and figure 16 show the example design waveform. figure 14 shows the typical sr driving signals and sr control signal sp-sn under ccm operation. figure 16 shows that the freewheeling sr is turned off by the lpc mechanism under dcm operation. figure 14. sr gate is driven by primary-side control signal under ccm operatio n figure 15. sin signal (rising edge) and sr control signal table 3. efficiency measurements at v ac =115v on 300w pc power with schottky diodes (fyp2006dn) load input watts(w) output watts(w) efficiency 100% 357.98 305.42 85.31% 50% 174.21 152.56 87.57% 20% 70.84 70.84 85.95% figure 15 and figure 17 shows the sin signal of fan6210 and sr control signals of fan6206 together. the efficiency test results are shown in table 3 and table 4. the significant difference between the sr mosfet and the schottky diode is shown in table 4. figure 16. freewheeling sr is turned off by lpc mechanism under dcm operation figure 17. sin signal (falling edge) and sr control signal table 4. efficiency measurements at v ac =115v on 300w pc power with srs (fdp5800) load input watts (w) output watts (w) efficiency vs. schottky diode 100% 347.02 305.43 88.01% +2.70% 50% 169.75 152.69 89.94% +2.40% 20% 69.24 61.04 88.15% +2.20%
AN-6206 application note ? 2010 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.0.0 ? 4/27/10 9 related resources fan6210 ? primary-side synchronous rectifier (sr) tr igger controller for dual forward converter fan6206 ? highly integrated dual-channel synchronous rec tification controller for dual-forward converter fan4801 ? pfc/pwm controller combination fan6751mr ? highly integrated green-mode pwm controller sg6520 ? pc power supply supervisors fdp5800 ? n-channel logic level powertrench? mosfet 60v,80a, 6m ? fcp20n60 / fcpf20n60 ? 600v n-channel mosfet 1n/fdll 914/a/b / 916/a/b / 4148 / 4448 ? small signal diode disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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